东枫科技

标签： USRP

  • USRP X410

    787272-01 | USRP X410 (4 TX/RX Channels, 400 MHz BW, Zynq US+ RFSoC ZU28DR) $ 29,950.00 USD

    The NI Ettus USRP X410 is a high-performance, multi-channel, Zynq US+ RFSoC based software defined radio (SDR) for designing and deploying next generation wireless systems.

    Overview

    The NI Ettus USRP X410 is a high-performance, multi-channel software-defined radio. The SDR  is designed for frequencies from 1 MHz to 7.2 GHz, tunable up to 8 GHz and features a two-stage superheterodyne architecture with 4 independent TX and RX channels capable of 400 MHz of instantaneous bandwidth each.  Digital interfaces for data offload and control include two QSFP28 interfaces capable of 100 GbE, a PCIe Gen3 x8 [1] interface, as well standard command, control, and debug interfaces: USB-C JTAG, USB-C console, Ethernet 10/100/1000. The USRP X410 is an all-in-one device built on the Xilinx Zynq Ultrascale+ ZU28DR RF System on Chip (RFSoC) with built-in digital up and down conversion and onboard Soft-Decision Forward Error Correction (SD-FEC) IP.

    Use the software of your choice 
    The NI Ettus USRP X410 is fully supported on the popular open-source USRP Hardware Driver (UHD) version 4.1 or later[2].  UHD 4.1 was designed to support the large data movement requirements imposed by the 400 MHz bandwidth and multiple channels onboard. The USRP X410 supports open-source SDR design flows such as C/C++ and GNU Radio, as well as LabVIEW FPGA [1]. Unlike other RFSoC-based systems, the USRP X410 is fully ready to port your previous UHD designs to take advantage of high-performance capabilities with a simple recompile.

    Networked / Stand-Alone Operation
    Since the USRP X410 is built on the ZU28DR RF System on Chip (RFSoC) device, it comes equipped with a quad-core ARM Cortex-A53 processing subsystem, clocked up to 1.2 GHz for stand-alone application requirements. Additionally, the RFSoC contains a dual-core ARM Cortex-R5 real-time processing unit for onboard monitoring and control.

    Built-In IP
    The onboard RFSoC on the USRP X410 contains more than twice the FPGA programmable logic resources than that of the previous generation X-series USRP devices. In addition, the ZU28DR comes with 8 soft-decision forward error correction (SD-FEC) hard IP cores, ideal for wireless communication systems. Given the high-speed nature of the built-in ADCs and DACs to the RFSoC, the Zynq device has 8 digital upconversion and digital down-conversion IP cores allowing for rapid in-band retuning or signal reduction.

    Multi-Radio Synchronization 
    Multi-radio clocking and timing synchronized operation is possible with the built-in GPSDO (GPS disciplined oscillator) or with the 10 MHz reference and 1 PPS (Pulse Per Second) input signal interfaces. Multi-Radio phase-aligned and phase-coherent operations are not supported, as RF chain LO import and export functionality is not supported on the USRP X410.

    [1] PCIe Gen3 x8 is only supported by NI-USRP and LabVIEW FPGA design flows
    [2] 100 GBE supported in UHD 4.2 or later

    Features

    • High channel density
    • Reliable and fault-tolerant deployment
    • Stand-alone (embedded) or host-based (network streaming) operation
    • Fully integrated and assembled (the USRP X410 does not support swappable daughtercards)
    • 1 MHz to 7.2 GHz frequency range (tunable up to 8GHz)
    • Up to 400 MHz of instantaneous bandwidth per channel
    • 4 RX, 4 TX in half-wide RU form factor
    • Xilinx Zynq-Ultrascale+ ZU28DR RFSoC
      • 12 bit ADC, 14 bit DAC
      • IQ Sample Clock rates up to 500 MS/s
      • Onboard SD-FEC, DDC, DUC
      • Quad-core ARM Cortex-A53 up to 1.2 GHz CPU
      • Dual-core ARM Cortex-A5 MPCore up to 500 MHz
    • Two QSFP28 ports (10 Gigabit Ethernet, 100 Gigabit Ethernet, Aurora)
    • Two iPass+™ zHD® Interfaces (PCIe Gen3 x 8)
    • RJ45 (1 GbE) [1]
    • 10 MHz Clock reference 
    • PPS time reference
    • Trig In/Out Interface
    • Built-in GPSDO 
    • Two FPGA Programmable GPIO Interfaces (HDMI)
    • 1 Type C USB host port 
    • 1 Type C USB port (serial console, JTAG) 
    • Watchdog timer
    • OpenEmbedded Linux
    • USRP Hardware Driver™ (UHD) open-source software API version 4.1.0 or later
    • RF Network on Chip (RFNoC™) FPGA development framework
    • Xilinx Vivado® 2019.1 Design Suite (license not included)
    • GNU Radio support is maintained by Ettus Research™ through GR-UHD, an interface to UHD distributed by GNU Radio

    [1] The RJ45 port is used for remote management of the device and does not support IQ streaming.

    Additional Resources

    Kit Contents

    • USRP X410
    • RJ45 Ethernet Cable
    • USB-C to USB-A cable
    • Power Supply

    Quotes and Sales

    Email：sales@tekdf.com

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  • USRP X310

    783145-01 | USRP X310 (KINTEX7-410T FPGA, 2 CHANNELS, 10 GIGE AND PCIE BUS) $ 10,396.00 USD

    The Ettus Research USRP X310 is a high-performance, scalable software defined radio (SDR) platform for designing and deploying next generation wireless communications systems.

    Overview

    The Ettus Research USRP X310 is a high-performance, scalable software-defined radio (SDR) platform for designing and deploying next-generation wireless communications systems. The hardware architecture combines two extended-bandwidth daughterboard slots covering DC – 6 GHz with up to 160 MHz of baseband bandwidth, multiple high-speed interface options (PCIe, dual 10 GigE, dual 1 GigE), and a large user-programmable Kintex-7 FPGA in a convenient desktop or rack-mountable half-wide 1U form factor. In addition to providing best-in-class hardware performance, the open source software architecture of X310 provides cross-platform UHD driver support making it compatible with a large number of supported development frameworks, reference architectures, and open source projects.  

    Operating SystemsLinuxWindows
    Development FrameworksGNU RadioXilinx Vivado 2015.2 Design Suite

    Table 1: Operating systems, development frameworks, and reference applications

    High-Performance User-Programmable FPGA

    At the heart of the USRP X310, the XC7K410T FPGA provides high-speed connectivity between all major components within the device including radio frontends, host interfaces, and DDR3 memory.  The default FPGA core provided with UHD provides all of the functional blocks for digital down-conversion and up-conversion, fine-frequency tuning, and other DSP functions allowing it to be interchangeable with other USRP devices using the UHD architecture.  The large Kintex-7 FPGA provides additional space for developers to incorporate custom DSP blocks and is compatible with a large number of USRP supported development frameworks, reference architectures, and open source projects.

    USRP N210USRP X300USRP X310
    FPGASpartan3 XC3SD3400AKintex 7-325TKintex 7 -410T
    Logic Cells53k328k406k
    Memory2,268 Kb16,020 Kb28,620 Kb
    Multipliers1268401540
    Clock Rate100 MHz200 MHz200 MHz
    Streaming Bandwidth per Channel (16-bit)25 MS/s200 MS/s200 MS/s

    Table 2: FPGA resource comparison

    Multiple High-Speed Interface Options

    The USRP X310 provides multiple interface options.  Out of the box, 1 GigE provides a convenient way to get started. For extended bandwidth and lower latency applications such as PHY/MAC research, PCIe x4 provides an efficient bus for deterministic operation. Applications using network recorders or multiple processing nodes can be best served by the 10 GigE interface option.

    Additional Features- GPSDO, GPIO, 1 GB DDR3, Synchronization

    The X310 includes many additional features that facilitate wireless system development.  On-board 1GB DDR3 with flexible access through the FPGA reference design supplements the FPGA resources with buffering and data storage memory.  An optional internal GPSDO provides a high-accuracy frequency reference, and global timing alignment to within 50 ns when synchronized to the GPS system.  The external GPIO connector allows users to control external components such as amplifiers and switches, accept inputs like event triggers, and observe debug signals.  The USRP X310 also includes an internal JTAG adapter that allows FPGA developers to easily load and debug new FPGA images.

    Features

    • Two wide-bandwidth RF daughterboard slots
      • Up to 160MHz bandwidth each (UBX or TwinRX)
      • Daughterboard selection covers DC to 6 GHz
    • Large customizable Xilinx Kintex-7 FPGA for high-performance DSP (XC7K410T)
    • Multiple high-speed interfaces
      • Dual 10 Gigabit Ethernet – 2x RX at 200 MSPs per channel
      • Dual 10 Gigabit Ethernet – 4x RX at 80 MSPs per channel
      • PCIe Express (Desktop) – 200 MS/s Full Duplex
      • ExpressCard (Laptop) – 50 MS/s Full Duplex
      • Dual 1 Gigabit Ethernet – 25 MS/s Full Duplex
    • UHD architecture provides compatibility with
      • GNU Radio
      • C++/Python API
      • Amarisoft LTE 100
      • OpenBTS
      • Other third-party software and frameworks
    • Flexible clocking architecture
      • Configurable sample rate
      • Optional GPS-disciplined OCXO
      • Coherent operation with OctoClock and OctoClock-G
    • Compact and rugged half-wide 1U form factor for convenient desktop or rack mount usage
    • Digital I/O accessible on the front panel for custom control and interfacing from the FPGA

    Additional Resources

    Included in This Kit:

    • USRP X310
    • 1 Gigabit Ethernet Cable
    • SFP Adapter for 1 GigE
    • Power Supply
    • USB 2.0 Cable for Internal JTAG Adapter
    • Four SMA-Bulkhead Cables
    • Getting Started Guide

    Quotes and Sales

    Email：sales@tekdf.com

    Wechat：dftech_info