UHD version 4.1 or later RFNoC GNU Radio C/C++ Python OpenEmbedded Linux on A53 NI-USRP 20.8 or later LabVIEW 2020 or later LabVIEW FPGA 2020 or later Matlab R2022a
1.5
时钟同步方式
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REF IN (clock reference input) PPS IN (PPS time reference) TRIG IN/OUT GPSDO included OCXO included
The NI Ettus USRP X410 is a high-performance, multi-channel, Zynq US+ RFSoC based software defined radio (SDR) for designing and deploying next generation wireless systems.
Overview
The NI Ettus USRP X410 is a high-performance, multi-channel software-defined radio. The SDR is designed for frequencies from 1 MHz to 7.2 GHz, tunable up to 8 GHz and features a two-stage superheterodyne architecture with 4 independent TX and RX channels capable of 400 MHz of instantaneous bandwidth each. Digital interfaces for data offload and control include two QSFP28 interfaces capable of 100 GbE, a PCIe Gen3 x8 [1] interface, as well standard command, control, and debug interfaces: USB-C JTAG, USB-C console, Ethernet 10/100/1000. The USRP X410 is an all-in-one device built on the Xilinx Zynq Ultrascale+ ZU28DR RF System on Chip (RFSoC) with built-in digital up and down conversion and onboard Soft-Decision Forward Error Correction (SD-FEC) IP.
Use the software of your choice The NI Ettus USRP X410 is fully supported on the popular open-source USRP Hardware Driver (UHD) version 4.1 or later[2]. UHD 4.1 was designed to support the large data movement requirements imposed by the 400 MHz bandwidth and multiple channels onboard. The USRP X410 supports open-source SDR design flows such as C/C++ and GNU Radio, as well as LabVIEW FPGA [1]. Unlike other RFSoC-based systems, the USRP X410 is fully ready to port your previous UHD designs to take advantage of high-performance capabilities with a simple recompile.
Networked / Stand-Alone Operation Since the USRP X410 is built on the ZU28DR RF System on Chip (RFSoC) device, it comes equipped with a quad-core ARM Cortex-A53 processing subsystem, clocked up to 1.2 GHz for stand-alone application requirements. Additionally, the RFSoC contains a dual-core ARM Cortex-R5 real-time processing unit for onboard monitoring and control.
Built-In IP The onboard RFSoC on the USRP X410 contains more than twice the FPGA programmable logic resources than that of the previous generation X-series USRP devices. In addition, the ZU28DR comes with 8 soft-decision forward error correction (SD-FEC) hard IP cores, ideal for wireless communication systems. Given the high-speed nature of the built-in ADCs and DACs to the RFSoC, the Zynq device has 8 digital upconversion and digital down-conversion IP cores allowing for rapid in-band retuning or signal reduction.
Multi-Radio Synchronization Multi-radio clocking and timing synchronized operation is possible with the built-in GPSDO (GPS disciplined oscillator) or with the 10 MHz reference and 1 PPS (Pulse Per Second) input signal interfaces. Multi-Radio phase-aligned and phase-coherent operations are not supported, as RF chain LO import and export functionality is not supported on the USRP X410.
[1] PCIe Gen3 x8 is only supported by NI-USRP and LabVIEW FPGA design flows [2] 100 GBE supported in UHD 4.2 or later
Features
High channel density
Reliable and fault-tolerant deployment
Stand-alone (embedded) or host-based (network streaming) operation
Fully integrated and assembled (the USRP X410 does not support swappable daughtercards)
1 MHz to 7.2 GHz frequency range (tunable up to 8GHz)
Up to 400 MHz of instantaneous bandwidth per channel
